The IOP (Internet Offload Processor) W7500P is the one-chip solution which integrates an ARM Cortex-M0, 128KB Flash and hardwired TCP/IP core & PHYfor various embedded application platform especially requiring ‘Internet of things’.
The TCP/IP core is a market-proven hardwired TCP/IP stack with an integrated Ethernet MAC. The Hardwired TCP/IP stack supports the TCP, UDP, IPv4, ICMP, ARP, IGMP and PPPoE which has been used in various applications for years. W7500P suits best for users who need Internet connectivity for application.
Key Features
ARM Cortex-M0
48MHz maximum frequency
Hardwired TCP/IP Core
8 Sockets
SRAM for socket: Max. 32KB
MII (Medium-Independent Interface)
PHY
IC Plus (IP101G)
Memories
Flash: 128 KB
SRAM: 16KB to 48 KB ( Min 16KB available if 32KB socket buffer is used, Max 48KB available if no socket buffer is used)
ROM for boot code: 6KB
Clock, reset and supply management
POR (Power-On Reset)
Internal Voltage Regulator : 3.3V to 1.5V
8-to-24MHz external crystal oscillator
Internal 8MHz RC Oscillator
PLL for CPU clock
ADC
12bit, 8ch, 1Msps
DMA
6-channel DMA controller
Peripheral supported: UARTs, SPIs
GPIO
34 I/Os (15 IO x 2ea, 4 IO x 1ea)
Debug mode
Serial Wire Debug (SWD)
Timer/PWM
1 Watchdog (32-bit down-counter)
4 Timers (32-bit or 16-bit down-counter)
8 PWMs (32-bit counter/timers with programmable 6-bit prescaler)
Communication Interfaces
3 UART (2 UARTs with FIFO and Flow Control, 1 simple UART)
2 SPI
2 I2C (Master/Slave, Fast-mode (400 kbps))
Crypto
1 RNG (Random Number Generator): 32-bit random number
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发表于2017-01-07 09:02:27
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