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凌阳凌通电机驱动专用芯片GPM8F3116A上市

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发表于2018-06-12 14:49:58 | 只看该作者
1# 电梯直达

GPM8F3116A购买链接:http://item.szlcsc.com/232704.html

GPM8F3132C购买链接:http://item.szlcsc.com/232703.html

资料下载请直接点击GPM8F3116A.pdf 

资料下载请直接点击GPM8F3132C.pdf 

  

General Description

The GPM8F3116A is a highly integrated microcontroller which integrates a pipelined 1T 8051 CPU, 512-byte XRAM, 256-byte IDM SRAM and 16K-byte program Flash. It includes 34 programmable multi-functional I/Os, Timer0/1/2, UART0, SPI (master), Motor control unit with built-in OP and comparators, audio and one up to 8-channel of 12-bit ADC for general-purpose application. It operates over a wide voltage range of 2.4V - 5.5V with different clock sources. It has two modes in power management unit. Moreover, there is one on-chip debug circuit with two pins to facilitate full speed in-system debug. The detail is described in the following sections.

Features

  • CPU
    • High speed, high performance 1T 8051
      • 100% software compatible with industry standard 8051
      • Pipeline RISC architecture enables to execute instructions 10 times faster than standard 8051
      • Up to 24.5MHz clock operation
  • Memories
    • 512 bytes XRAM
    • 256 bytes internal Data Memory (IDM) SRAM
    • 16K bytes Flash with high endurance
      • Minimum 200,000 program/erase cycles
      • Minimum 20 years data retention
    • Programming read only level for software security
  • Clock Management
    • Internal oscillator: 24.5MHz±2% @ 2.4V~5.5V
    • External clock input max 24.5MHz
    • Crystal input with 32768Hz or 1MHz~25MHz
  • Power Management
    • 1 STOP mode for power saving
    • 1 IDLE mode for only peripheral operation
  • Interrupt Management
    • 17 interrupt sources
    • Up to 6 external interrupt sources
  • Reset Management
    • Power On Reset (POR)
    • Low Voltage Reset (LVR)
    • Pad Reset (PAD_RST)
    • Watchdog Reset (WDT_RST)
    • Software Reset (S/W_RST)
    • Stop Mode Reset (STOP_RST)
    • Miss Clock Reset (MISS_CLK_RST)
    • Flash Related Error Reset (FLASH_ERR_RST)
  • Programmable Watchdog Timer
    • A time-base generator
    • An event timer
    • System supervisor
  • I/O Ports
    • Max. 34 multifunction bi-directional I/Os
    • Each incorporate with pull-up resistor, pull-down resistor, output high, output low or floating input, depending on programmer''s settings on the corresponding registers
    • I/O ports with 20mA current sink
    • I/O ports with 8mA current drive
  • Two 16-bit Timer/Counter (Timer 0/1)
    • Timer mode with clock source selectable
    • Auto reload 8-bit timers
    • Externally gated event counters
  • One Powerful Timer 2 with 16-bit Compare/Capture Unit
    • Timer mode with clock source selectable
    • Auto-reload 16-bit timers
    • Externally gated event counters
    • Event capturing
    • Pulse width modulation and measurement
  • UART0
    • One synchronous mode
    • Three asynchronous modes
  • SPI (master mode)
    • Programmable phase and polarity of master clock
    • Programmable master SPI_CLK clock frequency
    • Max SPI clock: 6.125MHz (FOSC /4) @24.5MHz
  • A/D converter
    • One 8-channel 8-bit resolution mode
    • One 8-channel 12-bit resolution mode
    • Max conversion clock: 6.125MHz (FOSC /4) @24.5MHz
  • Motor Control Unit
    • Programmable dead-time control
    • Built-in four comparators and OP contro
    • Built-in protective circuits
    • 16-bit capture unit control
  • Audio Module
    • 24KHz output or 32KHz output @24.5MHz
  • Debug Unit


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